As the semiconductor industry introduces new generations of integrated circuits (IC's) having higher performance and providing greater functionality, the density of the elements that form the ICs is increased, while the dimensions, sizes, and spacing between the individual components or elements are reduced. These device geometries having smaller dimensions are creating new manufacturing challenges.
For example, a continuous challenge in the semiconductor memory industry is to decrease the size of memory cell components in order to increase the packing density of the DRAM chip. Over the last few device generations, DRAM manufacturers have developed alternative cell layouts that reduce the area occupied on the chip. The latest designs allow a significant increase in density by burying the word line in the silicon substrate, then fabricating the bit line (also known as the digit line) and capacitor on top to form a vertical stack. Such devices are also known as buried word line (BWL) devices.
In such a memory device, the bit line and the capacitor are often fabricated over the surface of the semiconductor substrate. Therefore, a cell contact is required to provide electrical connection between the bit line and the active area of the semiconductor substrate, a landing pad is required to accommodate the capacitor, and another cell contact is required to provide electrical connection between the landing pad and the active area of the semiconductor substrate.
However, the formation of the landing pad involves several complicated steps. Furthermore, as integrated circuit designs become denser, it becomes more difficult to form the landing pads separate from each other in the array.
This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.